Challenges in Automotive ASIC Test

By Preeti Prasher
Principal ASIC Test Architect

 

In the world of semiconductor, having a great concept, a great design, is only the first step.  Ensuring the integrity of that design post-manufacturing and to scale is an equally important next chapter.  In automotive, there is a clear trend towards higher complexity, cutting-edge electronic systems.  Without ensuring that individual circuit components perform with the highest reliability, the overall system failure in time (FIT) rates would surely increase.

Balancing extreme cost pressures in the wake of added electronics while maintaining high mean time between failures (MTBFs) has led to a period of innovation for the design of automotive integrated circuits (ICs), as well as a renaissance in how we test them.  The automotive industry mandates higher test coverage and the ability to foresee lifetime failures at time zero.  With end customers demonstrating a low tolerance for cost adders, ASIC test engineers ultimately find themselves stuck in a contradiction between more tests and shorter test times with lower test costs.

Today’s automotive market and corresponding ISO 26262 standard demand the highest levels of functional safety (FuSa), especially in the field of advanced driver assistance systems (ADAS) and autonomous driving (AD).  This has led to an additional stage of self-test and monitoring once the chip is already in the field.  This new market requirement necessitates test considerations at every stage in application-specific IC (ASIC) development and the execution of a strategic test plan from day one that will ensure the confidence of Tier 1s and OEMs when moving forward with a product.

  • Key on: the driver is still in park and the ASIC needs to run some self-tests to ensure all related systems are go. 
  • Key off: the ASIC has a window to run diagnostics and ensure its continued functionality. 
  • Scheduled testing: over some driving interval, the ASIC needs to ensure its own reliability and flag any concerns regarding loss of function. 

 

When producing chips for the automotive industry, reliability and uniformity of each die, each package, is a top design and manufacturing goal.  This requires partnerships with like-minded suppliers who know you demand the best at all levels.  Hitting test and yield targets starts with alignment to a fab providing the competitive technology node needed and a low defect density (D0).  The efficacity of this first manufacturing step combined with the execution of a design-for-test (DFT) concept is verified at wafer probe (WP).

This initial test insertion can be leveraged to provide data across voltage and temperature corners, not only ensuring the robustness of the design over a vast operating range but in some cases, also to weed out early-life reliability failures (ELFRs) using burn-in (BI) and/or stress voltage testing.  In addition, using advanced statistical methods and screening, atypical die and wafers can also be removed to ensure the highest reliability of a product going forward.

Packaging wafers meeting the high standards of tight data distribution within tightly controlled limits, final test (FT) then provides the next test insertion where the quality of wafer screening is ensured while also removing possible defects introduced in assembly.  Final test provides an opportunity to fine tune or enhance the overall test coverage number and to ensure that the product being shipped meets the very high standards of the automotive industry.

In depth characterization of the design across process, voltage and temperature (PVT) corners will ensure ASIC performance is not compromised by expected variation in the production and operation lifecycle.  Correlation to a bench or systems setup will further guarantee the test program’s ability to anticipate and screen for real world applications.  Qualification tests will further confirm that all the careful planning and execution of a test plan translate to an ASIC that will stand the tests of time, mechanical and environmental rigours and all foreseeable hazards.  Lessons learned during qualification are leveraged by introducing time zero test screening guardbands that monitor for observed and understood drifts or lifetime degradation.

The road to certification requires careful scheduling, attention to detail, root cause analysis of each drift, and most importantly a learning that is carried forward to the next circuit design.  Successful execution in ASIC Test is not only measured by final shipment to the customer, but includes all the intermediate steps starting with DFT in the concept phase, selection of the optimal device technology for fabrication, choosing the right automated test equipment (ATE), designing high performance test hardware, correlating every measurement to a design requirement, a simulation result or system-level expectation, and finally ensuring that each device belongs to a controlled population.

This ultimately translates to a datasheet that customers can rely on to roll out their own next revolutionary product.

Key on: Test…

Key off: Test…

Key on: Set “Check ASIC” light